1. Field of the Invention
This invention relates to integrated circuit manufacturing and more particularly to position-selective and material-selective etching of silicon.
2. Description of the Relevant Art
Fabrication of an integrated circuit is a complex process involving numerous steps. To form a metal-oxide-semiconductor (MOS) transistor, for example, a gate dielectric is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. A gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. Such transistors are connected to each other and to terminals of the completed integrated circuit using conductive interconnect lines.
A pervasive trend in modem integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modem day processes employ features, such as gate conductors and interconnects, which have less than 0.3 xcexcm critical dimension. As feature size decreases, the sizes of the resulting transistors as well as those of the interconnects between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
This trend toward reduced feature sizes imposes severe demands on the reliable operation of the resulting transistors or other electronic devices. Reduction of feature sizes necessitates a xe2x80x9cscalingxe2x80x9d down of many device dimensions. As gate conductor widths decrease, for example, other transistor dimensions must also decrease in order to maintain proper transistor operation. Early MOSFET scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. For example, a maximum value of MOSFET subthreshold current can be maintained while feature sizes shrink, by decreasing any or all of several quantities, including gate oxide thickness, operating voltage, depletion width, and junction depth, by appropriate amounts. Such reductions in device dimensions greatly increase the manufacturing accuracy required to form devices which operate properly.
One area of a modem transistor at risk for reliability problems is the gate dielectric. Gate dielectric thicknesses are continually decreasing, driven in part by the device scaling described above. The increased transistor drive current which can be achieved with thinner gate dielectrics is another reason for decreases in gate dielectric thickness. Current gate dielectric thicknesses are therefore typically a few tens of angstroms, or less. Such thin dielectric films are susceptible to breakdown when subjected to the electric fields applied across the gate dielectric during transistor operation. Pinholes or thickness nonuniformities occurring in the gate dielectric are especially likely to cause dielectric breakdown.
Other areas of a transistor in which reliability problems may occur are the contacts made to silicon-based portions of the transistor. The source and drain of the transistor are junctions formed in a silicon substrate, and the transistor gate is typically formed from polycrystalline silicon, or polysilicon. To help in forming a low-resistance contact to such a source, drain or gate region, a metal silicide is often formed on the upper surface of the region. Such a silicide is formed by depositing a metal, typically titanium or cobalt, over the surface of the silicon on which the silicide is to be formed. The substrate is then heated so that the metal reacts with underlying silicon to form a silicide. Modem transistors employ increasingly shallow source and drain junctions to comply with scaling requirements. It is therefore important in many applications that the thickness of a silicide formed at the surface of such a junction be controlled so that the silicide does not extend down through the entire source or drain region, causing a short circuit of the source or drain to the substrate. A high degree of control over the silicide formation process is therefore required.
In order to maintain reliable circuit operation and acceptable yields of working circuits in light of the problems which may be caused or exacerbated by shrinking feature sizes, the ability to carefully examine device structures is important. The device structures examined may be actual devices at various stages of manufacture, or may be test structures used to optimize particular subprocesses involved in the fabrication. Actual imaging of the device structures examined is particularly desirable in many cases. For example, imaging of the corresponding portions of a device is well-suited to observation of quantities such as layer thickness, thickness uniformity, and interface structure. Surface morphology of a layer in a device structure may also be examined using imaging techniques. For example, pinholes in an oxide layer may be visible by imaging of the surface of the layer.
One of the highest-resolution imaging techniques available is transmission electron microscopy (TEM). A TEM image is created by transmission of high energy (about 60-350 keV) electrons through a very thin sample (a few atomic layers thick). The minimum feature size that can be imaged using a microscopy technique is generally somewhat larger than the wavelength of radiation used, because of diffraction and interference effects. The high electron energies used in TEM correspond to low electron wavelengths, as low as about 0.04 angstroms. The resulting feature sizes resolvable may be as small as one or two angstroms, making TEM a very xe2x80x9chigh-resolutionxe2x80x9d technique. There is a price to be paid for this high resolution, however. The thin samples required must be prepared by exacting ion milling techniques which may take several hours.
Scanning electron microscopy (SEM) is another electron-based imaging technique which typically requires minimal sample preparation and can be performed much more rapidly than TEM imaging. An SEM operates by creating a beam of electrons which are accelerated to energies ranging from several hundred to several thousand electron volts. The electron beam is focused to a small diameter and repeatedly scanned across a region of interest of a sample. As the beam strikes the sample""s surface, lower-energy secondary electrons are emitted. The yield of secondary electrons depends on many factors, such as the work function of the material, the topography of the sample, and the curvature of the surface. Because different materials may have significantly different work functions, the yield of secondary electrons may be used as a contrast mechanism to distinguish between different materials on a surface. Because changes in topography affect secondary electron yield, one may similarly measure a change in height along the sample""s surface. Electron current resulting from the surface-emitted secondary electrons is detected and used to correspondingly control the intensity of pixels on a monitor attached to the SEM. An image of the region being studied is formed by synchronously scanning the electron beam and the screen of the monitor.
The lower-energy electrons used in SEM make it a lower-resolution technique than TEM. Feature sizes on the order of ten angstroms may be resolved by SEM, however, giving the technique a resolution adequate for many aspects of semiconductor device examination. A more significant shortcoming of SEM as compared to TEM may be that interfaces between materials can be more difficult to detect. This is particularly true in the case of interfaces between materials with some similarity in composition, such as silicon/silicide interfaces.
Another difficulty with SEM observations, as well as with other forms of microscopy, is that the area of interest for examination may be buried beneath another portion of the sample. For example, it may be desirable to examine the gate dielectric of a transistor that has failed electrical testing, to look for pinholes or thickness nonuniformities in the dielectric. This might best be accomplished by scanning the electron beam in an SEM over the upper surface of the dielectric. Unfortunately, the dielectric upper surface is not accessible, since it is covered by the gate during fabrication of the transistor.
One approach to the problem of accessing buried layers for examination is known as xe2x80x9cdeprocessingxe2x80x9d or xe2x80x9cdelayeringxe2x80x9d, in which layers of an integrated circuit are removed so that buried layers may be exposed. This layer removal is typically accomplished using either dry etching or wet etching. There are some problems associated with the delayering approach, however. For example, the etch processes typically used may not have sufficient selectivity to avoid etching of very thin layers, such as gate dielectrics which may have thickness of less than 50 angstroms. Furthermore, the wet and dry etch processes remove all exposed portions of the layer to be etched. If delayering is desired only for a particular transistor or portion of a circuit, formation of a mask layer is needed to protect other portions of the circuit. The photolithography and etching processes typically used to form such a mask layer are time-consuming, add complexity to the failure analysis process, and increase the potential for contamination or defect generation. Another problem with the delayering approach is that air exposure of the sample is often required in the interval between the delayering and characterization of the exposed layer. This air exposure may result in oxidation and/or contamination of the sample, which may alter the layer before it can be characterized.
It would therefore be desirable to enhance the observability of layers such as dielectrics and silicides using SEM or other examination techniques, and to improve detection of interfaces between such layers and adjacent materials. It would further be desirable to develop a method for uncovering surfaces of buried layers for examination. The desired method for uncovering buried layers should avoid problems associated with air exposure in the interval between uncovering and characterization of a buried layer.
The problems outlined above are addressed by a method in which silicon may be selectively removed from a semiconductor device structure, while other materials, such as dielectrics, metals, and silicides are retained. In addition to this material selectivity, the method is also position-selective, so that the silicon is removed only in desired areas. A silicon-containing sample is loaded into a vacuum chamber having electron beam generation and positioning capability. The chamber is pumped down to a pressure in the 10xe2x88x927 millibar range. The sample may be imaged using the electron beam, and the electron beam may be positioned at a desired location, before placement of a shutter preventing the beam from impinging upon the sample. Xenon difluoride (XeF2) gas is introduced into the chamber in the vicinity of the sample, typically using a flow rate such that the chamber pressure increases to the 10xe2x88x925 millibar range. At this flow rate, no etching of the sample results from the XeF2 exposure. When the electron beam is unshuttered and allowed to impinge upon the sample in the presence of the XeF2 flow, however, silicon surfaces contacted by the electron beam are selectively etched.
This etching may be material-selective, in that silicon is etched, while other materials, including dielectrics, metals and silicides, are not. Furthermore, the etching may be position-selective, in that etching occurs only for silicon in contact with the electron beam. This combination of material-selective and position-selective etching may allow, for example, very precise examination of selected individual transistors within an integrated circuit. The electron beam controlled etching is also believed to be substantially anisotropic, with etching occurring largely in the direction of the beam.
For the purposes of this disclosure, xe2x80x9csiliconxe2x80x9d represents a semiconducting material comprised predominantly of silicon atoms. The silicon may be monocrystalline, polycrystalline, or amorphous. Although the silicon may be doped with impurity atoms, materials having concentrations of other atoms which are approximately equal to or greater than the concentration of silicon atoms are not considered to be xe2x80x9csiliconxe2x80x9d. Such materials not considered to be silicon include, for example, silicon oxides and metal suicides. These materials having large concentrations of other atoms are often non-semiconducting materials.
Use of much higher XeF2 pressures, on the order of a few millibar, is known to allow material-selective etching of silicon over dielectrics and metals, with no electron beam applied. This higher-pressure XeF2 etching method is often used in the fabrication of micro-electro-mechanical systems (MEMS) devices. Use of the higher XeF2 pressures may not allow position-selective etching, however. Because silicon etching takes place without application of an electron beam, etching may occur over the entire exposed silicon area of the device, rather than at the position in contact with an electron beam. The etching is also very isotropic in this case, so that control over sidewall profiles and aspect ratios may be difficult. Furthermore, the rate of etch and amount etched are believed to be more difficult to control using such a higher-pressure XeF2 etch, because the pressure of the XeF2 is believed to be difficult to control precisely. This control difficulty may arise because XeF2 is a solid at room temperature and pressure, subliming into a gas at pressures below about 4 torr, or about 5.3 torr. In the lower-pressure electron-beam controlled method recited herein, however, the precise pressure of XeF2 may be less important, because the etch rate is believed to be largely controlled by the electron beam energy and current. In addition, use of higher XeF2 pressures may lead to increased safety risks, because XeF2 is known to react with moisture to produce hydrofluoric acid, which is toxic and necessitates careful safety precautions.
Low pressures of XeF2 in combination with an ion beam have been used to obtain position-selective silicon etching. However, use of this ion beam-enhanced technique has been found to remove some of the material selectivity of the XeF2 etch. For example, low pressures of XeF2 (10xe2x88x925 millibar range) may be used in conjunction with an ion beam to etch silicon dioxide (xe2x80x9coxidexe2x80x9d) selectively over metals. This is in contrast to the method recited herein in which an electron beam is used and oxide is not believed to be etched. Ion beam enhanced XeF2 etching has also been found to etch cobalt silicide, while the electron beam enhanced method does not.
In embodiments of the method recited herein for which the sample has exposed silicon surfaces, electron-beam controlled XeF2 etching may be used to remove the silicon in selected areas such that underlying portions of the sample are exposed. This embodiment may allow, for example, an upper surface of a gate dielectric to be exposed by removal of an overlying polysilicon gate. In this way, the gate dielectric surface could be examined for the presence of pinholes or other morphological defects.
In embodiments for which silicon portions of the sample are buried below or behind other materials, a position-selective removal of a portion of the overlying materials may be combined with the electron-beam controlled silicon etch. For example, an opening may be formed through a transistor gate structure including a silicide layer over a polysilicon layer over a gate dielectric over monocrystalline silicon. The opening is preferably formed using a position-selective method such as ion milling or ion-beam controlled etching. In addition to the silicide layer at the top of this gate structure, the underlying silicon and dielectric layers are exposed in cross-section in the sidewalls of the opening. Electron-beam controlled silicon etching may then be employed to etch the silicon layers back from the sidewalls of the opening. In this way, upper and/or lower edges of the silicide and the gate dielectric are exposed by removal of the adjacent silicon. This may allow ready detection of the upper and lower edges of the silicide and gate dielectric, and thereby provide enhanced ability to measure the corresponding layer thickness and examine the interface profiles using SEM.
In addition to selectively etching silicon over other materials, the electron beam enhanced XeF2 etch recited herein also shows selectivity between different forms of silicon. For example, polysilicon may be etched much more rapidly than monocrystalline silicon in some embodiments of the method. This may be useful for embodiments in which it is desirable to remove polysilicon while leaving nearby monocrystalline silicon largely intact. As an example, a polysilicon gate conductor could be removed, exposing the underlying gate dielectric, while leaving the monocrystalline silicon substrate beneath the gate dielectric intact. Retention of the substrate may provide mechanical stability allowing the sample to be characterized by alternate methods. For example, atomic force microscopy (AFM), in which a probe held close to a surface is scanned with angstrom-level resolution, may be used to detect small steps on the surface of the sample which may indicate the locations of thin layers such as gate dielectric layers.
In embodiments for which SEM is used to image the sample after the electron-beam-controlled silicon etching described above, the method recited herein provides the possibility of performing the etching and imaging in the same chamber. Imaging is typically performed during the etch process, and may be performed before and/or after etching. Imaging and etching in the same chamber may be advantageous for samples which may be oxidized or contaminated by exposure to the ambient outside the vacuum chamber. Alternatively, the sample may be removed from the vacuum chamber after selective silicon etching in some embodiments, for imaging or other examination at a different location. In some embodiments, removal of silicon in the vicinity of a layer to be examined may make the sample more stable against changes (such as oxidation) upon transfer out of the vacuum chamber.
In addition to the applications described above, the position-selective and material-selective etching of silicon described herein may be applied to manufacturing of silicon-containing devices. Examples may include selective trimming of silicon structures such as gate conductors, or selective removal of silicon for other applications in the manufacture of electronic devices or MEMS devices.
In addition to the method described above, an examination structure for semiconductor manufacturing and failure analysis is contemplated herein. A device structure including a silicon layer and a layer formed from a different material is configured upon a semiconductor substrate. The different material may include a dielectric, a metal and/or a metal silicide. An opening formed in the silicon layer exposes a portion of an upper or lower surface of the different material layer. In one embodiment of the examination structure, an upper surface of a gate dielectric layer is exposed by an opening in an overlying polysilicon layer. The morphology of the exposed upper surface of the gate dielectric may be examined by various techniques, such as SEM and AFM. In an alternative embodiment, openings are formed both in a silicon layer overlying a gate dielectric and a silicon layer underlying the gate dielectric. In this way, a portion of the gate dielectric is an isolated thin membrane which may be examined by electron microscopy or other techniques. Information which may be available from such an examination includes, for example, dielectric thickness, dielectric thickness uniformity, and quality of the dielectric surface morphology.
In another embodiment of the examination structure, an opening formed in the silicon layer exposes a portion of the lower surface of an overlying silicide layer. The exposed surface of the silicide facilitates measurement of the silicide thickness using SEM or other microscopy techniques. The profile of the silicide lower surface may also provide information as to the profile of the interface between the silicide and the original underlying silicon. Measurement of the thickness of a silicide or dielectric layer by SEM is facilitated using examination structures such as those described above. Fabrication and SEM examination of such structures is believed to allow a thickness measurement to be obtained in about one hour or less. By contrast, obtaining such a thickness measurement using TEM may take significantly longer.